A simulation methodology for assessing the impact of spatial/pattern dependent interconnect parameter variation on circuit performance
- 23 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 01631918,p. 133-136
- https://doi.org/10.1109/iedm.1997.650217
Abstract
In this paper, we illustrate a methodology for determining the impact of interconnect pattern dependent variation on circuit performance. The methodology helps enable first pass prediction and can handle large layouts using methods which are reasonably compatible with existing CAD tools. We illustrate the relative utility of the methodology using two case studies. Both studies are drawn from industrial relevant problems: unwanted skew in a balanced clock tree and capacitance variation of a critical net in an SRAM array.Keywords
This publication has 0 references indexed in Scilit: