A fast square-rooting algorithm using a digital signal processor

1 January 1987

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in Proceedings of the IEEE

Vol. 75 (2) , 262-264
https://doi.org/10.1109/PROC.1987.13728

Abstract

The computation of square roots is required in signal processing applications, such as adaptive filtering using transversal filters or lattice filters, spectral estimation, and many other fields of engineering sciences. Actually, all the existing digital signal processors (DSP) have a multiplier-accumulator. We present a simple binary algorithm for square-rooting using a processor with multiplier. Only shifts, additions, and multiplications are used and unlike the Newton-Raphson approach, divisions are not necessary. The method can also be interesting for the computation of divisions. The algorithm has been implemented in 16-bit fixed-point arithmetic on a TMS32010 DSP processor. The computational requirements are compared with the Newton-Raphson method. The fixed-point code of the algorithm written in TMS32010 Assembly language is also given.

Keywords

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