VLSI implementation of an image compression algorithm with a new bit rate control capability

1 January 1992

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. 5 (15206149) , 669-672 vol.5
https://doi.org/10.1109/icassp.1992.226507

Abstract

An image compression algorithm with a new bit rate control capability is presented. The bit rate control technique is developed for use in conjunction with the JPEG baseline image compression algorithm. The new method is an extension of the previously developed algorithm which is implemented in the Zoran 031 image compression chip set. The chip set comprises a discrete cosine transform (DCT) processor and an image compression coder/decoder. Both methods and the chip set are discussed in detail.

Keywords

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