Design of Reliable Synchronous Sequential Circuits
- 1 May 1975
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-24 (5) , 567-570
- https://doi.org/10.1109/T-C.1975.224262
Abstract
Fail-safe synchronous sequential machines produce safeside outputs when failures occur within the machine. This correspondence presents a procedure to design such machines using a modification of the on-set equation form originally presented by Tohma et al. [1] and later improved by Diaz et al. [2]. A systematic procedure for state assignment and next-state equation derivation, using partition theory, is presented. From this method an easily calculated upper bound on the number of gates required-to realize a fail-safe circuit is derived.Keywords
This publication has 6 references indexed in Scilit:
- Fault-Tolerant Asynchronous Sequential MachinesIEEE Transactions on Computers, 1974
- Asynchronous Sequential Machines Designed for Fault DetectionIEEE Transactions on Computers, 1974
- On-Set Realization of Fail-Safe Sequential MachinesIEEE Transactions on Computers, 1974
- Improved State Assignment Selection TestsIEEE Transactions on Computers, 1972
- Realization of Fail-Safe Sequential Machines by Using a k-out-of-n CodeIEEE Transactions on Computers, 1971
- State Assignments for Asynchronous Sequential MachinesIEEE Transactions on Computers, 1971