Limits on multiple instruction issue
- 1 April 1989
- journal article
- conference paper
- Published by Association for Computing Machinery (ACM) in ACM SIGARCH Computer Architecture News
- Vol. 17 (2) , 290-302
- https://doi.org/10.1145/68182.68209
Abstract
This paper investigates the limitations on designing a processor which can sustain an execution rate of greater than one instruction per cycle on highly-optimized, non-scientific applications. We have used trace-driven simulations to determine that these applications contain enough instruction independence to sustain an instruction rate of about two instructions per cycle. In a straightforward implementation, cost considerations argue strongly against decoding more than two instructions in one cycle. Given this constraint, the efficiency in instruction fetching rather than the complexity of the execution hardware limits the concurrency attainable at the instruction level.Keywords
This publication has 8 references indexed in Scilit:
- The ZS-1 central processorPublished by Association for Computing Machinery (ACM) ,1987
- Instruction issue logic for high-performance, interruptable pipelined processorsPublished by Association for Computing Machinery (ACM) ,1987
- An Instruction Issuing Approach to Enhancing Performance in Multiple Functional Unit ProcessorsIEEE Transactions on Computers, 1986
- Look-Ahead ProcessorsACM Computing Surveys, 1975
- Percolation of Code to Enhance Parallel Dispatching and ExecutionIEEE Transactions on Computers, 1972
- On the Number of Operations Simultaneously Executable in Fortran-Like Programs and Their Resulting SpeedupIEEE Transactions on Computers, 1972
- Detection and Parallel Execution of Independent InstructionsIEEE Transactions on Computers, 1970
- An Efficient Algorithm for Exploiting Multiple Arithmetic UnitsIBM Journal of Research and Development, 1967