An algorithm for locating logic design errors
- 4 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Discusses the problem of locating logic design errors, and proposes an algorithm to solve it. Based on the results of logic verification, the authors introduce an input pattern for locating design errors. The pattern contains only one Boolean variable X/X and is used to sensitize the design errors. An algorithm for locating single design errors with the input patterns has been developed. Experimental results have shown the effectiveness of the input patterns and the algorithm for locating single design errors.<>Keywords
This publication has 6 references indexed in Scilit:
- Proving circuit correctness using formal comparison between expected and extracted behaviourPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Evaluation and improvement of Boolean comparison method based on binary decision diagramsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Locating functional errors in logic circuitsPublished by Association for Computing Machinery (ACM) ,1989
- Logic design verification via test generationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- A logic verifier based on Boolean comparisonPublished by Association for Computing Machinery (ACM) ,1986
- Boolean Comparison of Hardware and FlowchartsIBM Journal of Research and Development, 1982