Transient latchup in bulk CMOS with a voltage-dependent well-substrate junction capacitance

1 March 1985

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices

Vol. 32 (3) , 717-720
https://doi.org/10.1109/T-ED.1985.22006

Abstract

Transient latchup in bulk CMOS with a voltage-dependent well-substrate junction capacitance under a voltage ramp is analyzed. It is found that even when the external voltage is ramping up, α1+ α2> 1, and both bipolar transistors are biased in the forward-active region, the circuit can still dynamically recover internally due to the inherently nonlinear character of the voltage-dependent substrate-well junction capacitance. Numerical results for the cases of linearly graded and step junctions are presented and some optimal conditions for preventing transient latchup are briefly discussed.

Keywords

ELECTROSTATICS
ELECTRODES
TEMPERATURE
VOLTAGE
CAPACITANCE
TESTING

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