A Six-Port 57GB/s Double-Pumped Nonblocking Router Core

27 July 2005

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 268-269
https://doi.org/10.1109/vlsic.2005.1469383

Abstract

A six-port four-lane 57GB/s router core features double-pumped crossbar channels and destination-aware channel drivers that dynamically configure based on the current flit destination. This enables 45% reduction in channel area, 23% overall chip area, and up to 3.8/spl times/ reduction in peak channel power, depending on router traffic patterns. In a 150nm six-metal process, the 12.2mm/sup 2/ core contains 1.9 million transistors and operates at 1GHz at 1.2 V.

Keywords

PAPER TECHNOLOGY
CMOS TECHNOLOGY
MICROPROCESSORS
VERY LARGE SCALE INTEGRATION
INTEGRATED CIRCUIT INTERCONNECTIONS
LAN INTERCONNECTION
FREQUENCY
PIPELINES
TIMING

This publication has 1 reference indexed in Scilit:

Virtual-channel flow control
IEEE Transactions on Parallel and Distributed Systems, 1992