High-Speed Transistorized Adder for a Digital Computer
- 1 December 1960
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IRE Transactions on Electronic Computers
- Vol. EC-9 (4) , 461-464
- https://doi.org/10.1109/tec.1960.5219885
Abstract
An adder is described that has been developed for the Floating Indexed Point Arithmetic Unit, FLIP, to be used in conjunction with GEORGE, the existing computer built at Argonne National Laboratory. The logic of the high-speed adder and the special circuits required are presented. The adder is parallel and its high speed is made possible by reducing the carry propagation time. Each bit of the adder contributes one transistor to make up a tall AND gate which reduces the carry propagation time to 0.2 μsec. Using this high-speed carry propagation and rather common RCTL transistor circuitry, it is possible to complete an addition in less than 0.25 μsec.Keywords
This publication has 3 references indexed in Scilit:
- Transistor Current Switching and Routing TechniquesIRE Transactions on Electronic Computers, 1960
- Fast logic using current-routing and switching techniquesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1960
- Fast Carry Logic for Digital ComputersIEEE Transactions on Electronic Computers, 1955