Modeling and characterization of CMOS-compatible high-voltage device structures

1 November 1987

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices

Vol. 34 (11) , 2335-2343
https://doi.org/10.1109/t-ed.1987.23241

Abstract

The design, implementation, and modeling of high-voltage MOS transistors in a Standard CMOS technology is described. High voltage n- and p-channel transistors, with breakdown voltages of 50 and 180 V, respectively, have been fabricated. A SPICE-compatible model for these transistors is described, and its accuracy verified by comparison with experimental results.

Keywords

MODELING
CMOS TECHNOLOGY
STRUCTURES
VOLTAGE
CMOS COMPATIBLE
STANDARD CMOS
COMPATIBLE HIGH
COMPATIBLE MODEL

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