Hybrid FPGA architecture

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Abstract
This paper1 proposes a new field-programmable architec- ture that is a combination of two existing technologies: Field Programmable Gate Arrays (FPGAs) based on LookUp Tables (LUTs), and Complex Programmable Logic Devices based on PALs/PLAs. The methodology used for development of the new architecture, called Hybrid FPGA, is based on analysis of a large set of benchmark circuits, in which we determine what types of logic resources best match the needs of the circuits. The proposed Hybrid FPGA is evaluated by manually technology mapping a set of cir- cuits into the new architecture and estimating the total chip area needed for each circuit, compared to the area that would be required if only LUTs were available. Preliminary results indicate that compared to LUT -based FPGAs the Hybrid offers savings of more than a factor of two in terms of chip area. Over the past several years, high capacity Field Programma- ble Devices (FPDs) have enjoyed a rapidly expanding mar- ket, and have become widely accepted for implementation of small to moderately large digital circuits. The two main types of FPDs, Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs) are both widely used, and each offers specific strengths. FPGAs that are programmed with SRAM technology are usually based on LookUp Tables (LUTs); their main strengths are very high total logic capacity, in the range of tens of thou- sands of equivalent logic gates, and good speed-perfor- mance of 10 to 50 MHz system clock rates. On the other hand CPLDs consist of multiple PLA-based blocks, in which the OR planes are partly fixed. Their characteristics include medium capacity, in the range of a few thousand gates, and ultra high speed-performance, sometimes in excess of 100 MHz system clock rate. In this paper, we suggest a new type of FPD that represents a marriage of FPGAs and CPLDs. The basis for this idea is that digital circuits are structured in such a way that parts of the circuit are well-suited for implementation using LUTs, while other parts can benefit more from the Product term- 1. This work was funded by Hewlett Packard based (Pterm-based) structures found in CPLDs. Compari- son with an architecture that has only LUTs indicates that the Hybrid FPGA Architecture (HFA) offers significant savings in terms of the total area. Also, the HFA creates the potential to reduce the depth of the circuit implemented in the FPGA, which may provide improvements in speed-performance. This paper is organized as follows: Section 2 discusses related research on architecture of FPDs, Section 3 describes our research motivation, which is based on the analysis of BenchMark (BM) circuits, Section 4 presents the invented architecture, Section 5 gives an estimate of area gain pro- vided by the HFA, and the last section contains final remarks.

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