Performance of output-buffered banyan networks with arbitrary buffer sizes
- 1 January 1991
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 701-710 vol.2
- https://doi.org/10.1109/infcom.1991.147574
Abstract
A report is presented on a queueing analysis and a simulation study of a switch fabric based on a buffered banyan structure whereby buffers are placed at the output links of each switching element. When buffers are located at the input links, it is well known that maximum throughput is limited to approximately 0.45 under a uniform input traffic pattern. This bottleneck is due to the head of the line (HOL) contention at each switching element and is intrinsic to input queueing. The authors propose a buffered banyan switch built from smaller knockout switches which are output-buffered switches. With small knockout switches as the basic switching elements, the complexity of the overall switch fabric is manageable and no internal clock speedup is required. Furthermore, it is shown that with the proposed output-buffered banyan switch, a maximum throughput of 1 can be achieved.Keywords
This publication has 8 references indexed in Scilit:
- Performance of buffered banyan networks under nonuniform traffic patternsIEEE Transactions on Communications, 1990
- Design of a broadcast packet switching networkIEEE Transactions on Communications, 1988
- Input Versus Output Queueing on a Space-Division Packet SwitchIEEE Transactions on Communications, 1987
- The Knockout Switch: A Simple, Modular Architecture for High-Performance Packet SwitchingIEEE Journal on Selected Areas in Communications, 1987
- Design of an integrated services packet networkPublished by Association for Computing Machinery (ACM) ,1985
- Performance Analysis of a Packet Switch Based on Single-Buffered Banyan NetworkIEEE Journal on Selected Areas in Communications, 1983
- The Performance of Multistage Interconnection Networks for MultiprocessorsIEEE Transactions on Computers, 1983
- Analysis and Simulation of Buffered Delta NetworksIEEE Transactions on Computers, 1981