A 15 ns 4 Mb CMOS SRAM

Publisher Website
Google Scholar
Abstract
A 4-Mb SRAM with 15-ns access time and selectable (*4/*1) bit organization based on a 0.55- mu m triple-polysilicon double-metal CMOS technology is discussed. To achieve 15-ns access time, a sense amplifier with input-controlled PMOS loads (ICPLs), Y-controlled bit line loads, and transfer word driver are used. A built-in voltage regulator is provided to reduce the internal supply voltage to 4 V. Either *4 or *1 bit organization can be selected electrically, without pin connection changes. In the 0.55- mu m triple-polysilicon double-metal CMOS technology, the first polysilicon (polycide) is used for gate electrodes, the second (silicide) for the VSS lines of memory cells, and the third for resistive loads. The first metal is used for bit lines, and the second for the main word lines. The gate oxide thickness is 15 mm and the gate length is 0.55 mu m/0.65 mu m (NMOS/PMOS). The cell size is 3.4*5.6 mu m. The chip size is 7.7*18.6 mm.<>

This publication has 2 references indexed in Scilit: