Hybrid silicon wafer-scale packaging technology

23 March 2005

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 166-167
https://doi.org/10.1109/isscc.1986.1156981

Abstract

Procedures developed for mounting ICs in holes in a silicon wafer and inter-connecting them, via two-level metalization, will be presented. The performance of the interconnections at high speeds will be compared with traditional hybrid assemblies.

Keywords

SILICON
PACKAGING
INTEGRATED CIRCUIT INTERCONNECTIONS
ETCHING
WIRE
WAFER BONDING
HIGH SPEED OPTICAL TECHNIQUES
OPTICAL INTERCONNECTIONS
ALUMINUM
ANISOTROPIC MAGNETORESISTANCE

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