Minimization of mechanical and chemical strain at dielectric-semiconductor and internal dielectric interfaces in stacked gate dielectrics for advanced CMOS devices
- 1 January 2001
- proceedings article
- Published by AIP Publishing in AIP Conference Proceedings
- Vol. 550 (1) , 154-158
- https://doi.org/10.1063/1.1354389
Abstract
This paper identifies fundamental aspects of Si-dielectric and internal dielectric interfaces that limit the ultimate performance of Si field effect transistor, FET, devices for scaled complementary metal oxide semiconductor, CMOS, integrated circuits. Three different interface limitations are discussed: i) residual suboxide bonding at Si-SiO 2 interfaces, ii) bond induced mechanical strain at Si-Si 3 N 4 and SiO 2 -Si 3 N 4 interfaces, and iii) charged defects associated with heterovalent bonding at Si-high-k oxide and silicate dielectric interfaces.Keywords
This publication has 0 references indexed in Scilit: