A VLSI Design of a Pipeline Reed-Solomon Decoder
- 1 May 1985
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-34 (5) , 393-403
- https://doi.org/10.1109/tc.1985.1676579
Abstract
A pipeline structure of a transform decoder similar to a systolic array is developed to decode Reed-Solomon (RS) codes. An important ingredient of this design is a modified Euclidean algorithm for computing the error-locator polynomial. The computation of inverse field elements is completely avoided in this modification of Euclid's algorithm. The new decoder is regular and simple, and naturally suitable for VLSI implementation. An example illustrating both the pipeline and systolic array aspects of this decoder structure is given for a (15,9) RS code.Keywords
This publication has 3 references indexed in Scilit:
- The VLSI Implementation of a Reed—Solomon Encoder Using Berlekamp's Bit-Serial Multiplier AlgorithmIEEE Transactions on Computers, 1984
- Bit-serial Reed - Solomon encodersIEEE Transactions on Information Theory, 1982
- The fast decoding of Reed-Solomon codes using Fermat theoretic transforms and continued fractionsIEEE Transactions on Information Theory, 1978