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Design of high speed MOS multiplier and divider using redundant binary representation
Home
Publications
Design of high speed MOS multiplier and divider using redundant binary representation
Design of high speed MOS multiplier and divider using redundant binary representation
SK
Shigeo Kuninobu
Shigeo Kuninobu
TN
Tamotsu Nishiyama
Tamotsu Nishiyama
HE
Hisakazu Edamatsu
Hisakazu Edamatsu
TT
Takashi Taniguchi
Takashi Taniguchi
NT
Naofumi Takagi
Naofumi Takagi
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1 May 1987
proceedings article
Published by
Institute of Electrical and Electronics Engineers (IEEE)
https://doi.org/10.1109/arith.1987.6158706
Abstract
No abstract available
Cited
Cited by 105 articles
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