Relations between Electrical Noise and Dislocations in Silicon

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Abstract
The effect of edge dislocations on electrical noise in n‐type silicon has been investigated. Parallel arrays of edge dislocations have been introduced by plastic deformation in vacuum at near 950°C, and the amount of dislocations introduced has been examined by etch pits. Electrical conductivity and noise measurements confirm the Shockley—Read model, according to which edge dislocations behave as lines of acceptors in semiconductors with the diamond structure. From the conductivity measurements, values of the fractional disturbed volume, ε, of the conductive sample are deduced in accordance with Read's theory. Noise results in dislocated samples show 1/f and g—r components differing from those of control samples obtained from the same ingot and also differing from samples subjected to the same heat treatment but without introduced dislocations. The g—r noise can be explained in terms of fluctuations in ε, which in turn are caused by fluctuations in the number of captured electrons at the dislocation sites. It is found that, in the temperature range 25°–170°C, for 200‐Ω·cm samples, the observed time constants and noise amplitudes are consistent with fluctuation phenomena associated with the dislocation sites acting as recombination centers. However, at near and below room temperature, trapping at the dislocation sites seems to be the primary cause of the observed noise behavior.