A static 4096-bit bipolar random-access memory
- 1 October 1977
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 12 (5) , 524-527
- https://doi.org/10.1109/JSSC.1977.1050946
Abstract
A description of a 23600 mil/SUP 2/, 35-ns 4096/spl times/1 bit bipolar RAM is presented. The historical evolution of density and performance of the 1024/spl times/1 forerunner along with advanced production and circuit techniques indicate the availability of an 11000 mil/SUP 2/, 10-ns, 4096/spl times/1 bipolar RAM by 1981.Keywords
This publication has 3 references indexed in Scilit:
- A 4K static clocked and nonclocked RAM designPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1977
- A fast 1024-bit bipolar RAM using JFET load devicesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1977
- A 1024-bit ECL RAM with 15-ns access timePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1976