Selective ion implantation to reduce power consumption in MOS integrated circuits

1 May 1978

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices

Vol. 25 (5) , 547-548
https://doi.org/10.1109/t-ed.1978.19128

Abstract

A method of using implantation to reducek'in selected MOS transistors on an LSI chip is described. An application of this technique is described where the power consumed in circuits such as memory cells is reduced without impairing other operating parameters.

Keywords

INTEGRATED CIRCUITS
ION IMPLANTATION
MEMORY CELLS
POWER CONSUMED
REDUCE POWER
SELECTIVE ION
USING IMPLANTATION
REDUCEK'IN SELECTED
SELECTED MOS

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