Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks

1 January 1996

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 107-113
https://doi.org/10.1109/fpga.1996.242437

Abstract

We present a new approach for FPGA testing that exploits the reprogrammability of FPGAs to create Built-In Self-Test (BIST) logic only during off-line test. As a result, BIST is achieved without area or performance penalties to the system function implemented by the FPGA, since the FPGA is reconfigured for normal system operation. An analysis of Look-Up Table (LUT) based FGPA architectures yields a general expression for the number of test sessions and establishes the bounds on FPGA logic resources required to minimize the number of BIST configurations required to completely test all of the programmable logic blocks of an FPGA.

Keywords

FIELD PROGRAMMABLE GATE ARRAYS
BUILT-IN SELF-TEST
PROGRAMMABLE LOGIC ARRAYS
PROGRAMMABLE LOGIC DEVICES
LOGIC TESTING
CIRCUIT TESTING
SYSTEM TESTING
LOGIC DEVICES
TEST PATTERN GENERATORS
PATTERN ANALYSIS

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