Minimizing width in linear layouts
- 26 December 2005
- book chapter
- Published by Springer Nature
- p. 478-490
- https://doi.org/10.1007/bfb0036931
Abstract
No abstract availableKeywords
This publication has 9 references indexed in Scilit:
- Topological bandwidthPublished by Springer Nature ,1983
- Polynomial time algorithms for the MIN CUT problem on degree restricted treesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1982
- Computer-aided design: Automating chip layout: New computer-based layout systems are faster than their human counterparts and produce designs that almost match those created manuallyIEEE Spectrum, 1982
- The complexity of searching a graphPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1981
- Dynamic-Programming Algorithms for Recognizing Small-Bandwidth Graphs in Polynomial TimeSIAM Journal on Algebraic Discrete Methods, 1980
- A dense gate matrix layout method for MOS VLSIIEEE Transactions on Electron Devices, 1980
- One-dimensional logic gate assignment and interval graphsIEEE Transactions on Circuits and Systems, 1979
- Complexity Results for Bandwidth MinimizationSIAM Journal on Applied Mathematics, 1978
- Large Scale Integration of MOS Complex Logic: A Layout MethodIEEE Journal of Solid-State Circuits, 1967