A pipelined associated memory implemented in VLSI
- 1 February 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 24 (1) , 28-34
- https://doi.org/10.1109/4.16298
Abstract
A memory system which rapidly chooses the stored item most closely matching a given input is fundamental to a number of recognition tasks. A memory architecture which performs this function is discussed. In addition, a measure of the quality of the selected (best matching) memory is generated. The architecture is capable of significant data throughput rates and is amenable to implementation using conventional digital VLSI fabrication process. These characteristics are demonstrated by a prototype device fabricated using the MOSIS 3- mu m CMOS design rules, which can compare more than two million 9-bit input works per second. Behavioral simulations demonstrate the applicability of the architecture to some basic recognition tasks.Keywords
This publication has 11 references indexed in Scilit:
- A high-speed string-search engineIEEE Journal of Solid-State Circuits, 1987
- A CMOS associative memory chip based on neural networksPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1987
- Connectionist Architectures for Artificial IntelligenceComputer, 1987
- VLSI implementation of a neural network memory with several hundreds of neuronsAIP Conference Proceedings, 1986
- An artificial neural network integrated circuit based on MNOS/CCD principlesAIP Conference Proceedings, 1986
- VLSI Arrays for Minimum-Distance ClassificationsPublished by Springer Nature ,1984
- Neural networks and physical systems with emergent collective computational abilities.Proceedings of the National Academy of Sciences, 1982
- Content-Addressable MemoriesPublished by Springer Nature ,1980
- Low-cost associative memoryIEEE Journal of Solid-State Circuits, 1972
- Integrated-circuit content-addressable memoriesIEEE Journal of Solid-State Circuits, 1970