A 1.2V, sub-0.09 μm gate length CMOS technology

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Abstract
CMOS technology for 1.2 V high performance applications is being scaled to sub-0.09 /spl mu/m physical nominal gate lengths and with effective gate dielectric thickness less than 2 nm to achieve the roadmap trend for high performance applications. For this technology, formation of the gate dielectric is by remote-plasma nitridation. To support the short target gate length, pocket implants, reduced energy drain extensions following gate re-oxidation, and implementation of high temperature, short-time anneal (spike anneal) of drain extension and source/drain implants is utilized. Dopant profiles are carefully tailored for reduced parasitic junction capacitance. In this work, for a nominal gate length of sub-0.09 /spl mu/m (post gate reoxidation), and gate dielectric thickness of 2.7 nm (nMOS), 3.0 nm (pMOS) (inversion at 1.2 V), nMOS and pMOS I/sub drive/ is 763 /spl mu/A//spl mu/m and 333 /spl mu/A//spl mu/m respectively, at 1.2 V with maximum I/sub off/=5 nA//spl mu/m. Gate-drain overlap in this work is /spl sim/210 /spl Aring//side and bottomwall junction capacitance is reduced to 0.8 fF//spl mu/m/sup 2/ (pMOS) and 1.1 fF//spl mu/m/sup 2/ (nMOS). With reduced parasitics and high drive current, the 1.2 V technology FOM (Figure-of-Merit) is >39 GHz, meeting the roadmap trend.

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