Timing verification of dynamically reconfigurable logic for the xilinx virtex FPGA series
- 24 February 2002
- conference paper
- Published by Association for Computing Machinery (ACM)
- p. 127-135
- https://doi.org/10.1145/503048.503068
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
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- The Garp architecture and C compilerComputer, 2000
- Methods of exploiting simulation technology for simulating the timing of dynamically reconfigurable logicIEE Proceedings - Computers and Digital Techniques, 2000
- Hardware-software co-design of embedded reconfigurable architecturesPublished by Association for Computing Machinery (ACM) ,2000