On a Pin Versus Block Relationship For Partitions of Logic Graphs
- 1 December 1971
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-20 (12) , 1469-1479
- https://doi.org/10.1109/t-c.1971.223159
Abstract
Partitions of the set of blocks of a computer logic graph, also called a block graph, into subsets called modules demonstrate that a two-region relationship exists between P, the average number of pins per module, and B, the average number of blocks per module. In the first region, P = KBr, where K is the average number of pins per block and 0.57 ≤ r ≤ 0.75. In the second region, that is, where the number of modules is small (i.e., 1-5), P is less than predicted by the above formula and is given by a more complex relationship. These conclusions resulted from controlled partitioning experiments performed using a computer program to partition four logic graphs varying in size from 500 to 13 000 circuits representing three different computers. The size of a block varied from one NOR circuit in one of the block graphs to a 30-circuit chip in one of the other block graphs.Keywords
This publication has 5 references indexed in Scilit:
- The Questions of Systems Implementation with Large-Scale IntegrationIEEE Transactions on Computers, 1969
- A justification of, and an improvement on, a useful rule for predicting circuit-to-pin ratiosPublished by Association for Computing Machinery (ACM) ,1969
- System Utilization of Large-Scale IntegrationIEEE Transactions on Electronic Computers, 1967
- Partitioning for large-scale integrationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1967
- System architecture for large-scale integrationPublished by Association for Computing Machinery (ACM) ,1967