A 3.3mW 12MS/s 10b pipelined ADC in 90nm digital CMOS
- 30 August 2005
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 278-279 Vol. 1
- https://doi.org/10.1109/isscc.2005.1493977
Abstract
A 10b pipelined ADC has been realized in a digital 90 nm CMOS technology using techniques such as switched opamps and switched-input buffers. Measurements show that this ADC samples at 12 MS/s achieving a peak SNDR of 52.6 dB using a 1.2 V supply. It consumes 3.3 mW and occupies 0.3 mm/sup 2/ core area.Keywords
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