Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation
- 24 August 2005
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 405-408
- https://doi.org/10.1109/dac.1996.545610
Abstract
No abstract availableKeywords
This publication has 9 references indexed in Scilit:
- Optimal sizing of high-speed clock networks based on distributed RC and lossy transmission line modelsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A fast algorithm for optimal wire-sizing under Elmore delay modelPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Clock routing for high-performance ICsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A sequential quadratic programming approach to concurrent gate and wire sizingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Optimal wiresizing under Elmore delay modelIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1995
- RC interconnect optimization under the Elmore delay modelPublished by Association for Computing Machinery (ACM) ,1994
- Reliable non-zero skew clock trees using wire width optimizationPublished by Association for Computing Machinery (ACM) ,1993
- An Applications Oriented Guide to Lagrangian RelaxationInterfaces, 1985
- The Transient Response of Damped Linear Networks with Particular Regard to Wideband AmplifiersJournal of Applied Physics, 1948