An experimental hardware neural network using a cascadable, analogue chipset
- 1 April 1995
- journal article
- circuit techniques-and-analysis
- Published by Taylor & Francis in International Journal of Electronics
- Vol. 78 (4) , 679-690
- https://doi.org/10.1080/00207219508926201
Abstract
An experimental hardware neural network built of cascadable, analogue CMOS test chips has been successfully trained by a host computer on the sunspot benchmark series using hardware-in-the-loop backpropagation learning. Comparisons are made with an ideal software net. Experiments show the advantage of training with recall-mode weight resolutions when having an extra ‘high’ precision weight representation for the weight updating. Hyperbolic tangent neuron outputs are used directly to calculate the neuron derivatives. To avoid false negative derivatives due to output offsets, the outputs are scaled. Considering hardware learning implementation, common output scaling is shown to be feasible.Keywords
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