Emulating a Complex Instruction Set Computer with a Reduced Instruction Set Computer

1 February 1987

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Micro

Vol. 7 (1) , 60-72
https://doi.org/10.1109/mm.1987.304939

Abstract

GaAs now allows up to 30K transistors per chip. With such a limitation, can you build a 32-bit CISC on a single GaAs chip? Yes, if you build a reduced instruction set computer and emulate the 32-bit CISC on it.

Keywords

This publication has 8 references indexed in Scilit:

An Introduction to GaAs Microprocessor Architecture for VLSI
Computer, 1986
Instruction Cache Replacement Policies and Organizations
IEEE Transactions on Computers, 1985
VLSI Processor Architecture
IEEE Transactions on Computers, 1984
A GaAs 4Kb SRAM with direct coupled FET logic
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1984
Solid state: Integrated circuits: The case for gallium arsenide: This superfast semiconductor holds great promise for high-speed computers, and manufacturing difficulties are now beginning to be overcome
IEEE Spectrum, 1983
Architecture of a VLSI instruction cache for a RISC
Published by Association for Computing Machinery (ACM) ,1983
Compilers and Computer Architecture
Computer, 1981
Comments on "the case for the reduced instruction set computer," by Patterson and Ditzel
ACM SIGARCH Computer Architecture News, 1980