A GaAs 4Kb SRAM with direct coupled FET logic

1 January 1984

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

Vol. XXVII, 46-47
https://doi.org/10.1109/isscc.1984.1156647

Abstract

A GaAs 4Kb × 1 SRAM with DCFL using self-aligned implantation for N+- layer technology will be discussed. The SRAM has been measured at a 5ns address access time with 700mW dissipation.

Keywords

GALLIUM ARSENIDE
RANDOM ACCESS MEMORY
FETS
LOGIC
READ-WRITE MEMORY
THRESHOLD VOLTAGE
POWER DISSIPATION
CIRCUIT SIMULATION
MESFETS
MONITORING

This publication has 1 reference indexed in Scilit:

GaAs LSI-directed MESFET's with self-aligned implantation for n⁺-layer technology (SAINT)
IEEE Transactions on Electron Devices, 1982