Timing optimization of combinational logic
- 6 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 5 references indexed in Scilit:
- MIS: A Multiple-Level Logic Optimization SystemIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Performance-Oriented Synthesis of Large-Scale Domino CMOS CircuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1987
- Delay optimization of combinational static CMOS logicPublished by Association for Computing Machinery (ACM) ,1987
- Synthesis and Optimization of Multilevel Logic under Timing ConstraintsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1986
- LSS: A system for production logic synthesisIBM Journal of Research and Development, 1984