A 100 MHz 4 Mb cache DRAM with fast copy-back scheme
- 2 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 148-149,
- https://doi.org/10.1109/isscc.1992.200455
Abstract
A 4-Mb cache DRAM (CDRAM) which integrates 16-kb SRAM as a cache memory and 4-Mb DRAM is described. The 4-Mb CDRAM features 100-MHz cache hit operation with an improved localized cache architecture. Circuits require only 7% more area than a conventional 4-Mb DRAM. There is 3* faster cache miss access over conventional copy back with fast copy back, as well as maximized mapping flexibility (applicable to direct mapping, set-associative, and full-associative). The block diagram of the 4-Mb CDRAM is shown along with a micrograph.<>Keywords
This publication has 2 references indexed in Scilit:
- A circuit design of intelligent CDRAM with automatic write back capabilityPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1990
- An eyperimental 1Mb cache DRAM with ECCPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1989