A circuit design of intelligent CDRAM with automatic write back capability
- 1 January 1990
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
The authors describe a unique intelligent memory based on a distributed CDRAM (cache DRAM) architecture, which consists of three hierarchical memory sections, DRAM, SRAM, and CAM, that constitute on-chip TAG. This architecture provides a high-performance intelligent main memory and a pin compatibility with high-speed address nonmultiplexed memories (DRAM, SRAM, and pseudo-SRAM). This RAM can be fabricated by the standard CMOS DRAM process with little area penalty. The intelligent CDRAM with an automatic write-back function can realize a short average read/write cycle time. The write-back operation without a complex controller minimizes the write cycle time drastically compared with write throughKeywords
This publication has 2 references indexed in Scilit:
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