High-performance devices for a 0.15- mu m CMOS technology
- 1 October 1993
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 14 (10) , 466-468
- https://doi.org/10.1109/55.244732
Abstract
Devices have been designed and fabricated in a CMOS technology with a nominal channel length of 0.15 mu m and minimum channel length below 0.1 mu m. In order to minimize short-channel effects (SCEs) down to channel lengths below 0.1 mu m, highly nonuniform channel dopings (obtained by indium and antimony channel implants) and shallow source-drain extensions/halo (by In and Sb preamorphization and low-energy As and BF/sub 2/ implant were used. Maximum high V/sub DS/ threshold rolloff was 250 mV at effective channel length of 0.06 mu m. For the minimum channel length of 0.1 mu m, the loaded (FI=FO=3, C=240 fF) and unloaded delays were 150 and 25 ps, respectively.Keywords
This publication has 4 references indexed in Scilit:
- Indium channel implant for improved short-channel behavior of submicrometer NMOSFETsIEEE Electron Device Letters, 1993
- A High Performance 0.25/spl mu/m CMOSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993
- A high-performance 0.25- mu m CMOS technology. II. TechnologyIEEE Transactions on Electron Devices, 1992
- Experimental technology and characterization of self-aligned 0.1µm-gate-length low-temperature operation NMOS devicesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1987