Storage hierarchy to support a 600 MHz G5 S/390 microprocessor
- 20 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Although a microprocessor's maximum frequency and internal design are important, the storage hierarchy is the primary reason for the large system performance improvement of the S/390 G5 compared to the G4. The improvement is achieved with an L2 cache, system controller and memory interface clocked at 1/4 the microprocessor frequency.Keywords
This publication has 3 references indexed in Scilit:
- IBM's S/390 G5 microprocessor designIEEE Micro, 1999
- S/390 Parallel Enterprise Server Generation 3: A balanced system and cache structureIBM Journal of Research and Development, 1997
- Shared-cache clusters in a system with a fully shared memoryIBM Journal of Research and Development, 1997