A new array architecture for parallel testing in VLSI memories

Publisher Website

13 January 2003

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/test.1989.82315

Abstract

No abstract available

Keywords

This publication has 2 references indexed in Scilit:

A Twisted Bit Line Technique for Multi-Mb Drams
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1988
A 90ns 1Mb DRAM with multi-bit test mode
Published by Institute of Electrical and Electronics Engineers (IEEE) ,1985