Scaling challenges and device design requirements for high performance sub-50 nm gate length planar CMOS transistors
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- 7 November 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 1 reference indexed in Scilit:
- Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET'sIEEE Electron Device Letters, 1997