Activation Energies of Thermal Annealing of Radiation-Induced Damage in N- and P-Channels of CMOS Integrated Circuits

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Abstract
Tempering and isothermal curves of annealing of radiation damage in p- and n-channels of both commercial, or "soft," and radiation-hardened, or J-process, samples of RCA CD4007A CMOS integrated circuits, irradiated with both Co-60 gamma-rays and 1 MeV electrons, have been determined. These experimental data were analyzed for activation energies of thermal annealing using two theoretical treatments, one of which is a new approach proposed here. The resulting activation energy distribution of p-channels of both the commercial and J-process exhibit a single peak centered at about 1eV, whereas the distributions of n-channels of the commercial process exhibit two distinct peaks centered at about 0.9 and 1.2eV. The activation energy distributions of n-channels of the J-process show three peaks centered at about 0.7, 1.0 and 1.3eV. The two peaks in the n-channels of the commercial devices are attributed to the double diffusion of phosphorus and boron in the formation of the p-well and the subsequent growth of the gate oxide using this silicon surface. If this reasoning is correct, then it follows that the radiation-induced charge trapping in the gate oxide occurs mainly around the impurity centers. The n-channels of the J-process exhibit considerable reverse annealing under elevated temperatures and large long-term room-temperature annealing as compared to p-channels. No differences in the annealing modes between devices irradiated with Co-60 gamma rays and 1 MeV electrons were observed.

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