Digitally-controlled PLL with pulse width detection mechanism for error correction
- 22 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 2 references indexed in Scilit:
- A 320 MHz, 1.5 mW at 1.35 V CMOS PLL for microprocessor clock generationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- MOS oscillators with multi-decade tuning range and gigahertz maximum speedIEEE Journal of Solid-State Circuits, 1988