A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme
- 1 February 1997
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 32 (2) , 289-291
- https://doi.org/10.1109/4.551926
Abstract
A high-speed ring oscillator is proposed for improved operation frequency over those based on the conventional n-stage inverter chain. The ring oscillator consists of inverters with negative delay elements that are derived from the ring oscillator circuit. The cell delay of the ring oscillator is smaller than a fundamental inverter delay. Simulations show that the resulting operating frequencies are 50% higher than those obtainable from the conventional approaches.Keywords
This publication has 4 references indexed in Scilit:
- A 150 MHz 0.6 μm BiCMOS superscalar microprocessorIEEE Journal of Solid-State Circuits, 1994
- Precise delay generation using coupled oscillatorsIEEE Journal of Solid-State Circuits, 1993
- A novel CMOS digital clock and data decoderIEEE Journal of Solid-State Circuits, 1992
- A 30-MHz hybrid analog/digital clock recovery circuit in 2- mu m CMOSIEEE Journal of Solid-State Circuits, 1990