A novel CMOS digital clock and data decoder

This publication has 5 references indexed in Scilit:

• PLL-based BiCMOS on-chip clock generator for very high-speed microprocessor
  IEEE Journal of Solid-State Circuits, 1991
• A monolithic CMOS 10 MHz DPLL for burst-mode data retiming
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1990
• A 30-MHz hybrid analog/digital clock recovery circuit in 2- mu m CMOS
  IEEE Journal of Solid-State Circuits, 1990
• An analog PLL-based clock and data recovery circuit with high input jitter tolerance
  IEEE Journal of Solid-State Circuits, 1989
• A novel precision MOS synchronous delay line
  IEEE Journal of Solid-State Circuits, 1985