A monolithic CMOS 10 MHz DPLL for burst-mode data retiming

Publisher Website

1 January 1990

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

https://doi.org/10.1109/isscc.1990.110191

Abstract

No abstract available

Keywords

This publication has 2 references indexed in Scilit:

A survey of digital phase-locked loops
Proceedings of the IEEE, 1981
Charge-Pump Phase-Lock Loops
IEEE Transactions on Communications, 1980