Speed-area-power optimization for DCFL and SDCFL class of logic using ring notation
- 31 August 1991
- journal article
- Published by Elsevier in Microprocessing and Microprogramming
- Vol. 32 (1-5) , 75-82
- https://doi.org/10.1016/0165-6074(91)90326-o
Abstract
No abstract availableKeywords
This publication has 1 reference indexed in Scilit:
- A 6.5-ns GaAs 20*20-b parallel multiplier with 67-ps gate delayIEEE Journal of Solid-State Circuits, 1990