Test set compaction for combinational circuits

This publication has 8 references indexed in Scilit:

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  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005
• COMPACTEST: A METHOD TO GENERATE COMPACT TEST SETS FOR COMBINATIONAL CIRCUITS
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2005
• Compacting randomly generated test sets
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• SOCRATES: a highly efficient automatic test pattern generation system
  IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
• SMART And FAST: Test Generation for VLSI Scan-Design Circuits
  IEEE Design & Test of Computers, 1986
• On the Complexity of Estimating the Size of a Test Set
  IEEE Transactions on Computers, 1984
• On the Acceleration of Test Generation Algorithms
  IEEE Transactions on Computers, 1983
• An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
  IEEE Transactions on Computers, 1981