Tiling with limited resources
- 14 July 1997
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 229-238
- https://doi.org/10.1109/asap.1997.606829
Abstract
International audienceIn the framework of perfect loop nests with uniform dependences, tiling has been extensively studied as a source-to-source program transformation. Little work has been devoted to the mapping and scheduling of the tiles on to physical processors. We present several new results in the context of limited computational resources, and assuming communication-computation overlap. In particular, under some reasonable assumptions, we derive the optimal mapping and scheduling of tiles to physical processorKeywords
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