Precise exceptions in asynchronous processors
- 13 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- No. 1522869X,p. 16-28
- https://doi.org/10.1109/arvlsi.2001.915547
Abstract
The presence of precise exceptions in a processor leads to complications in its design. Some recent processor architectures have sacrificed this requirement for performance reasons at the cost of software complexity. We present an implementation strategy for precise exceptions in asynchronous processors that does not block the instruction fetch when exceptions do not occur; the cost of the exception handling mechanism is only encountered when an exception occurs during execution - an infrequent event.Keywords
This publication has 4 references indexed in Scilit:
- The design of an asynchronous MIPS R3000 microprocessorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- The Mips R10000 superscalar microprocessorIEEE Micro, 1996
- Compiling communicating processes into delay-insensitive VLSI circuitsDistributed Computing, 1986
- Communicating sequential processesCommunications of the ACM, 1978