A CMOS four-quadrant analog multiplier with single-ended voltage output and improved temperature performance
- 1 January 1991
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 26 (9) , 1293-1301
- https://doi.org/10.1109/4.84947
Abstract
No abstract availableKeywords
This publication has 13 references indexed in Scilit:
- A voltage-controllable linear MOS transconductor using bias offset techniqueIEEE Journal of Solid-State Circuits, 1990
- A ±5-V CMOS analog multiplierIEEE Journal of Solid-State Circuits, 1987
- New four-quadrant CMOS analogue multiplierElectronics Letters, 1987
- A class of analog CMOS circuits based on the square-law characteristic of an MOS transistor in saturationIEEE Journal of Solid-State Circuits, 1987
- Wide dynamic range four-quadrant CMOS analog multiplier using linearized transconductance stagesIEEE Journal of Solid-State Circuits, 1986
- A CMOS Four-Quadrant Analog MultiplierIEEE Journal of Solid-State Circuits, 1986
- CMOS voltage to current transducersIEEE Transactions on Circuits and Systems, 1985
- A high density CMOS processPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985
- A four-quadrant NMOS analog multiplierIEEE Journal of Solid-State Circuits, 1982
- A high-performance monolithic multiplier using active feedbackIEEE Journal of Solid-State Circuits, 1974