Wide dynamic range four-quadrant CMOS analog multiplier using linearized transconductance stages
- 1 December 1986
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 21 (6) , 1120-1122
- https://doi.org/10.1109/jssc.1986.1052656
Abstract
No abstract availableKeywords
This publication has 8 references indexed in Scilit:
- A 20-V four-quadrant CMOS analog multiplierIEEE Journal of Solid-State Circuits, 1985
- Integrated MOS four-quadrant analog multiplier using switched capacitor technology for analog signal processor ICsIEEE Journal of Solid-State Circuits, 1985
- Analogue four-quadrant CMOS multiplier with resistorsElectronics Letters, 1985
- Four quadrant multiplier core with lateral bipolar transistor in CMOS technologyElectronics Letters, 1985
- Four-quadrant CMOS analogue multiplierElectronics Letters, 1984
- Design of linear CMOS transconductance elementsIEEE Transactions on Circuits and Systems, 1984
- A four-quadrant NMOS analog multiplierIEEE Journal of Solid-State Circuits, 1982
- A precise four-quadrant multiplier with subnanosecond responseIEEE Journal of Solid-State Circuits, 1968