Latch-Up Elimination in Bulk CMOS LSI Circuits
- 1 January 1980
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Nuclear Science
- Vol. 27 (6) , 1735-1738
- https://doi.org/10.1109/tns.1980.4331097
Abstract
Inherent in the structure of bulk CMOS integrated circuits are four-layer parasitic paths that can become activated into a low impedance, high-current state, i.e., latch-up. Activation can be accomplished by photocurrents generated by ionizing radiation or by terminal over-voltage spikes. As loss of functionality or device destruction can result, latch-up is undesirable. This paper describes a method of latchup prevention by the use of n on n+ starting material. A graphical analysis is presented that aids in the understanding of the latch-up mechanism and provides insight into the elimination of that state. Experimental data in support of the model is presented.Keywords
This publication has 3 references indexed in Scilit:
- Latch-Up Control in CMOS Integrated CircuitsIEEE Transactions on Nuclear Science, 1979
- Neutron Irradiation for Prevention of Latch-Up in MOS Integrated CircuitsIEEE Transactions on Nuclear Science, 1979
- Prevention of CMOS Latch-Up by Gold DopingIEEE Transactions on Nuclear Science, 1976